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PIC32MX3XX/4XX
10.0
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
? Automatic Word-Size Detection:
- Transfer Granularity, down to byte level
- Bytes need not be word-aligned at source
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 31. “Direct Memory
Access (DMA) Controller” (DS61117) of
the “PIC32MX Family Reference Man-
ual” , which is available from the Microchip
web site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The PIC32MX Direct Memory Access (DMA) controller
is a bus master module useful for data transfers
between different devices without CPU intervention.
The source and destination of a DMA transfer can be
any of the memory mapped modules existent in the
PIC32MX (such as Peripheral Bus (PBUS) devices:
SPI, UART, I 2 C?, etc.) or memory itself.
Following are some of the key features of the DMA
controller module:
? Four Identical Channels, each featuring:
- Auto-Increment Source and Destination
Address Registers
- Source and Destination Pointers
- Memory to Memory and Memory to
Peripheral Transfers
and destination
? Fixed Priority Channel Arbitration
? Flexible DMA Channel Operating Modes:
- Manual (software) or automatic (interrupt)
DMA requests
- One-Shot or Auto-Repeat Block Transfer
modes
- Channel-to-channel chaining
? Flexible DMA Requests:
- A DMA request can be selected from any of
the peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request
source
- A DMA transfer abort can be selected from
any of the peripheral interrupt sources
- Pattern (data) match transfer termination
? Multiple DMA Channel Status Interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half-full
- DMA transfer aborted due to an external
event
- Invalid DMA address generated
? DMA Debug Support Features:
- Most recent address accessed by a DMA
channel
- Most recent DMA channel to transfer data
? CRC Generation Module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
FIGURE 10-1:
INT Controller
DMA BLOCK DIAGRAM
System IRQ
Peripheral Bus
Address
Decoder
Channel 0
Control
SE
I 0
L
Channel 1
Control
I 1
Y
Bus
Interface
Device Bus + Bus Arbitratio n
I 2
Global Control
(DMACON)
Channel n
Control
I n
SE
L
Channel Priority
Arbitration
? 2010 Microchip Technology Inc.
DS61143G-page 97
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